D-wave architecture

Illustrations to follow. This information is taken directly from D-wave corporate website.

http://www.dwavesys.com/en/deep-dive.html

 

 

Experimental Investigation of an Eight Qubit Unit Cell
in a Superconducting Optimization Processor
Part I: Hardware Design
Richard Harris, Fabio Altomare, Andrew Berkley, Paul Bunyk,
Suz Gildert, Mark Johnson, Eric Ladizinsky, Trevor Lanting
and Elena Tolkacheva
D-Wave Systems Inc.
Burnaby, BC Canada
September 2010
Primary Reference: Harris et al., Phys. Rev. B 82, 024511 (2010)
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 1 / 45
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 2 / 45
Introduction to Quantum Annealing (QA)
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary

An otherwise free spin-1/2 subjected to a magnetic field:
H=0 H=-gµBBsz
B=Bz
Spin-1/2
c c
c
c
,
Energy eigenstates are coincident with the spin basis (| .i,| .i),
independent of field orientation.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 4 / 45
Introduction to Quantum Annealing (QA)
Ising Spin in a Magnetic Field
Consider a spin-1/2 at the center of a tetragonal crystal unit cell. Crystal
field (symmetry) constrains spin to point along longest axis.
H=Hcf H=-gµB(Bllsz+Btsx)
Bll
c c
c c
,
Bt
Spin-1/2 in a
tetragonal crystal
a +b
c c b -a
Field orientation matters:
For Bt ?B||, ground state is (| .i + | .i)/v2.
For Bt ?B||, ground state is either | .i or | .i.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 5 / 45
Introduction to Quantum Annealing (QA)
Ising Spin Glass (ISG)
A non-magnetic crystal with randomly distributed spin-1/2 dopants.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 6 / 45
Introduction to Quantum Annealing (QA)
Ising Spin Glass (ISG)
A non-magnetic crystal with randomly distributed spin-1/2 dopants.
J12
J23
J13
HISG =X
i ,j>i
J.σ(i )
z σ(j)
z
Spin-spin interactions give rise to interactions J. with random sign and
magnitude. Ground state is disordered (glassy).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 6 / 45
Introduction to Quantum Annealing (QA)
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use Bt to perform quantum annealing (QA):
BtpJij/gµB
J12
J23
J13
HQSG ?-gµBBtXi
σ(i )
x
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 7 / 45
Introduction to Quantum Annealing (QA)
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use Bt to perform quantum annealing (QA):
Bt ~ Jij/gµB
J12
J23
J13
HQSG =X
i ,j>i
J.σ(i )
z σ(j)
z – gµBBtXi
σ(i )
x
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 7 / 45
Introduction to Quantum Annealing (QA)
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use Bt to perform quantum annealing (QA):
Bt`Jij/gµB
J12
J23
J13
HQSG ?X
i ,j>i
J.σ(i )
z σ(j)
z
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 7 / 45
Introduction to Quantum Annealing (QA)
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use Bt to perform quantum annealing (QA):
Bt=0
J12
J23
J13
HISG = X
i ,j>i
J.σ(i )
z σ(j)
z
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 7 / 45
Introduction to Quantum Annealing (QA)
Finding the Ground State via Quantum Annealing (QA)
Finding the ground state of an ISG is experimentally challenging. One
approach is to use Bt to perform quantum annealing (QA):
Bt=0
J12
J23
J13
For QA experiments on a bulk ISG (LiHoxY1-xF4) see Brooke et al.,
Science 284, 779 (1999).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 7 / 45
Introduction to Quantum Annealing (QA)
Application of Ising Spin Glass Physics
There are commercial applications, such as optimization and machine
learning, that involve solving problems of the form
E(~s) = -Xi
hi si +X
i ,j>i
K. si sj , (1)
where si = ?1 and -1 = hi ,K. = +1. The optimal solution ~sgs minimizes
E(~s). Substituting si . σ(i )
z yields an ISG Hamiltonian
HISG(t)
E0(t)
= -Xi
hiσ(i )
z +X
i ,j>i
K.σ(i )
z σ(j)
z , (2)
where E0(t) has units of energy. Now |~sgsi is the ground state of an ISG.
Applying a global transverse field . (t) allows one to implement QA:
HQSG(t)
E0(t)
= -Xi
hiσ(i )
z +X
i ,j>i
K.σ(i )
z σ(j)
z – (t)Xi
σ(i )
x . (3)
See Farhi et al., Science 292, 472 (2001) for details.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 8 / 45
Introduction to Quantum Annealing (QA)
Why Implement QA?
Reason 1:
QA is a physically motivated method of harnessing quantum resources.
Moreover, thermodynamics need not always thwart the intended
computation [see Amin et al. Phys. Rev. Lett. 100, 060503 (2008)].
Reason 2:
Valuable real-world optimization problems can be cast as an Ising spin
glass. Why not build hardware that excels at solving such problems?
Reason 3:
Implementing QA is an excellent warmup exercise before implementing
even harder architectures. For example, universal adiabatic quantum
computation [see Biamonte and Love, Phys. Rev. A 78, 012352 (2008)].
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 9 / 45
Analog Components of a QA Processor
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 10 / 45
Analog Components of a QA Processor
Implementing a Programmable QSG
D-Wave builds programmable hardware whose low energy Hamiltonian
HQSG(t)
E0(t)
= -Xi
hiσ(i )
z +X
i ,j>i
K.σ(i )
z σ(j)
z – (t)Xi
σ(i )
x
can be used for solving optimization problems. We have adopted a
top-down approach in which the QSG architecture drives the design.
Specific ingredients that must be incorporated into the hardware:
Quantum Ising spins (qubits) that can be annealed ( ).
Local biases on each spin (hi ).
Tunable couplings between spins (K. ).
A means of unambiguously reading the final spin configuration |~si.
Additional constraints:
The design must be robust against realistic fabrication variations.
The design must be realistically scalable up to 1000뭩 of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 11 / 45
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 12 / 45
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
rf-SQUID Flux Qubit
A Josephson junction of critical current Ic
in a superconducting loop of inductance
Lbody . Loop is subjected to an external
flux bias x
q ?0/2 (0 = h/2e ).
Ic
Fq x
jq
Lbody c
c
Persistent current I p
q . phase drop .q:
I p
q = Ic sin (.q) =
0.q/2π – x
q
Lbody
-3 -2 -1 0 1 2 3
0
5
10
15
20
Iq (mA) p
E/h (GHz)
c c
Fq = F0/2 x
-3 -2 -1 0 1 2 3
0
5
10
15
20
Iq (mA) p
E/h (GHz)
c
c
Fq t F0/2 x
Bistable potential supports two countercirculating states | .i and | .i.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 13 / 45
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
Flux Qubits as Quantum Ising Spins
Low energy Hamiltonian is that of a qubit or a quantum Ising spin:
Hq = –
1
2
[oqσz + qσx ]
oq = 2
I p
q
x
q – 0/2
-3 -2 0 2 3
0
5
10
15
20
Iq (mA) p
E/h (GHz)
eq
1eq
2+Dq
2
Fq t F0/2 x
-|Iq| p +|Iq| p
Parameter Qubit Quantum Ising Spin
oq Bias Energy Longitudinal Field (?gµB)
q Tunneling Energy Transverse Field (?gµB)

I p
q
Persistent Current gµB

I p
q
and q are the defining properties of any flux qubit.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 14 / 45
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
CCJJ Flux Qubit
We use a compound-compound Josephson junction (CCJJ) rf SQUID in
our designs. One can define a net phase .q across the entire CCJJ:
I1 I2
FL
x Fq x
jq
I3 I4
FR x
Fccjj
x
Lbody
Lccjj/2 Lccjj/2
Ic
Fq x
jq
Lbody @
Ic=Fcn(FL,FR,Fccjj) x x x
Key advantages of the CCJJ rf SQUID flux qubit:
The flux xccjj allows one to tune q (transverse field).
The flux biases (x
L,x
R) can be used to mitigate the eects of
variations in junction critical current, I1 6= I2 6= I3 6= I4.
One can homogenize the net Ic (x
L,x
R) between multiple CCJJ flux
qubits by carefully choosing (x
L,x
R).
See Harris et al. Phys. Rev. B, 81 134510 (2010) for details.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 15 / 45
Analog Components of a QA Processor Qubits (Quantum Ising Spins)
CCJJ Flux Qubit Parameters
The CCJJ flux qubit provides tunable q(xccjj) [transverse field].
However,
I p
q xccjj
[gµB] is also altered by this control.
Hq = –
1
2
[oqσz + qσx ] , oq = 2
I p
q
x
q – 0
q
-0.63 -0.625 -0.62 -0.615 -0.61
105
106
107
108
109
1010
©xccjj/©0
¢q/h (Hz)
Bistable
1QLZ
2QLZ
©xc
cjj Locked
2QLZ
©xc
cjj Unlocked
-0.65 -0.64 -0.63 -0.62 -0.61 -0.6 -0.59
0
0.25
0.5
0.75
1
1.25
1.5
Bistable Monostable
©xccjj/©0
|Ip
q | (µA)
q0
q1
q2
q3
q4
q5
q6
q7
Living with this latter phenomenon adds complexity to implementing QA
with flux qubits [see Harris et al., Phys. Rev. B 82, 024511 (2010)].
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 16 / 45
Analog Components of a QA Processor Interqubit Couplers
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 17 / 45
Analog Components of a QA Processor Interqubit Couplers
Interqubit Couplers
Mij
Coupler
{
Qubit i Qubit j
Fco
x Mco,l Mco,r
3 2 1 0 1 2 3
0
5
10
15
20
3 2 1 0 1 2 3
0
5
10
15
20
0 0.2 0.4 0.6
-4
-2
0
2
+MAFM
-MAFM
©xco/©0
Mij (pH)
A two-junction rf SQUID provides a sign and magnitude tunable mutual
inductance
M. = Mco,lMco,rχ. (xco) ,
where χ. (xco) represents a tunable linear magnetic susceptibility (units of
H-1). Maximum antiferromagnetic (AFM) coupling strength is denoted as
MAFM. We generally restrict operation -MAFM . M. = MAFM.
See Harris et al. Phys. Rev. B, 80 052506 (2009) for details.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 18 / 45
Analog Components of a QA Processor Interqubit Couplers
A Network of Inductively Coupled Flux Qubits
Combining multiple qubits and couplers yields a QSG. The low energy
Hamiltonian for general bias conditions can be written as
H0(t) = –
1
2Xi
hoi (t) σ(i )
z + q(t) σ(i )
x i +X
i ,j>i
J. (t)σ(i )
z σ(j)
z . (4)
oi (t) = 2
I p
q (t)
xi
(t) – 0i

J. = M.
I p
q (t)
2
Eq. (4) has terms of the same symmetry as the QSG Hamiltonian:
H0(t)
E0(t)
= -Xi
hiσ(i )
z +X
i ,j>i
K.σ(i )
z σ(j)
z – (t)Xi
σ(i )
x (5)
One then needs to choose a convenient E0(t) to map problem instances
(hi , K. ) onto the hardware controls xi
(t) and M. . Living with flux qubits
(not 몉eal?quantum Ising spins) requires additional hardware . . .
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 19 / 45
Analog Components of a QA Processor Persistent Current Compensation
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 20 / 45
Analog Components of a QA Processor Persistent Current Compensation
Mapping ISG Problems onto Hardware (1)
Let us complete the mapping of problem instance specifications onto
hardware settings: (hi ,K. ) . (xi
(t),M. ). Define E0(t) = MAFM|I p
q (t)|2,
where MAFM is the maximum AFM interqubit coupling.
H0(t)
E0(t)
= -Xi
hiσ(i )
z +X
i ,j>i
K.σ(i )
z σ(j)
z – (t)Xi
σ(i )
x (6a)
Simply solving for QSG parameters hi , K. , and (t) yields the following:
hi =
oi (t)
2E0(t)
=
xi
(t) – 0i
MAFM|I p
q (t)|
(6b)
K. =
J. (t)
E0(t)
=
M.
MAFM
(6c)
(t) =
q(t)
2E0(t)
=
q(t)
2MAFM|I p
q (t)|2 (6d)
Consider the forms of hi , K. , and (t) carefully . . .
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 21 / 45
Analog Components of a QA Processor Persistent Current Compensation
Mapping ISG Problems onto Hardware (2)
First, look at the transverse component that is meant to facilitate QA:
(t) =
q(t)
2E0(t)
=
q(t)
2MAFM|I p
q (t)|2
-0.63 -0.625 -0.62 -0.615 -0.61
105
106
107
108
109
1010
©xccjj/©0
¢q/h (Hz)
Bistable
1QLZ
2QLZ
©xc
cjj Locked
2QLZ
©xc
cjj Unlocked
-0.65 -0.64 -0.63 -0.62 -0.61 -0.6 -0.59
0
0.25
0.5
0.75
1
1.25
1.5
Bistable Monostable
©xccjj/©0
|Ip
q | (µA)
q0
q1
q2
q3
q4
q5
q6
q7
Sweeping the flux bias xccjj from right to left in time t ensures that
(t = 0) ?1 and (t = tf ) ?1, thus implementing QA.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 22 / 45
Analog Components of a QA Processor Persistent Current Compensation
Mapping ISG Problems onto Hardware (3)
Next, look at the problem instance parameters:

K. =
J. (t)
E0(t)
=
M.
MAFM
hi =
oi (t)
2E0(t)
=
xi
(t) – 0i
MAFM|I p
q (t)|
-0.65 -0.64 -0.63 -0.62 -0.61 -0.6 -0.59
0
0.25
0.5
0.75
1
1.25
1.5
Bistable Monostable
©xccjj/©0
|Ip
q | (µA)
q0
q1
q2
q3
q4
q5
q6
q7
The problem parameters hi and K. are supposed to be time-independent.
This comes out very naturally for K. , but not so for hi .
There is an imbalance in hi since oi (t) .
I p
q (t)
while J. (t) .
I p
q (t)
2.
One needs to correct this with xi
(t) – 0i
.
I p
q (t)
.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 23 / 45
Analog Components of a QA Processor Persistent Current Compensation
Persistent Current Compensator (IPC)
Flux bias needed to implement persistent current compensation on qubit i :
xi
(t) = hi ?MAFM|I p
q (t)| + 0i
. (7)
0i
is a trivial static flux oset (more later). Supply the time-dependent
portion via an external current bias Ig (t) = α|I p
q (t)| (where α ?1)
through a tunable mutual inductance

Mi (xI
PC ) = hiMAFM/α (8)
Ig(t)
Mi { IPC
FIPC
x
Fq x
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
©x
Ip,i/©0
Mi (pH)
+MAFM/®
-MAFM/®
M0
M1
M2
M3
M4
M5
M6
M7
For complete details, see Harris et al., Phys. Rev. B 82, 024511 (2010).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 24 / 45
Analog Components of a QA Processor Inductance Tuner
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 25 / 45
Analog Components of a QA Processor Inductance Tuner
Inductance Tuner
Interqubit couplers inductively load the qubits. Changing coupler χi will
change Lq, thus altering q(xccjj) (transverse field) and
I p
q (xccjj)
(gµB).
c1 cn
FLT FLT
x
Mco,1 Mco,n
= Lbody
Lccjj/2 Lccjj/2
-0.4 -0.2 0 0.2 0.4
0
4
8
12
16
©x
LT /©0
±Lq (pH)

Provide an inductance tuner (LT) with which one can compensate Lq to
render q(xccjj) and
I p
q (xccjj)
independent of coupler settings.
Lq = Lbody + Lccjj/4 +
n
Xi
=1
M2
co,iχi +
LLT
cos πx
LT /0
(9)
See Harris et al. Phys. Rev. B, 81 134510 (2010) for details.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 26 / 45
Analog Components of a QA Processor Readout
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 27 / 45
Analog Components of a QA Processor Readout
QFP-Enabled Readout
Qubits are localized into | .i or | .i by the QA algorithm (q . 0). We
use a quantum flux parametron (QFP) as a type of preamplifier of the
qubit뭩 final state to boost the fidelity to in excess of 99.99% in practice.

iro(t)
QFP
vro(t)
Qubit dc SQUID
Flatch
x
Fro
x
c
c
Basic readout operation:
1 QFP is annealed in the presence of | .i or | .i by ramping xl
atch from
0/2 to 0, thus latching QFP state into its own | .i or | .i.
2 멛atched?state of QFP is then read by a dc SQUID using
conventional switching measurement.
See Berkley et al., arXiv:0905.0891 (2009) for details.
(accepted in Supercond. Sci. Technol.)
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 28 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 29 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Ingredients for a QA Processor
The complete qubit has a CCJJ, L tuner (LT), I p
q
compensator (IPC),
and readout (RO). Each qubit is subjected to two time-dependent current
biases, Ig (t) that provides the
I p
q
-compensation signal and ICCJJ that
provides the annealing signal xccjj(t).
Fccjj
x
Ig
CCJJ
LT
IPC
RO
Coupler Qubit

Qubits need to be arranged on a lattice connected by couplers to form a
QA processor . . .
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 30 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Eight Qubit Unit Cell
q0
RO
CCJJ
LT
IPC

Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q0 . q3 spaced evenly apart.
Overlay four horizontal qubits q4 . q7.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 31 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Eight Qubit Unit Cell
q0 q1 q2 q3
RO
CCJJ
LT
IPC

Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q0 . q3 spaced evenly apart.
Overlay four horizontal qubits q4 . q7.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 31 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Eight Qubit Unit Cell
q0 q1 q2 q3
q4
q5
q6
q7
RO
CCJJ
LT
IPC

Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q0 . q3 spaced evenly apart.
Overlay four horizontal qubits q4 . q7.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 31 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Eight Qubit Unit Cell
q0 q1 q2 q3
q4
q5
q6
q7
RO
CCJJ
LT
ICO
IPC

Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q0 . q3 spaced evenly apart.
Overlay four horizontal qubits q4 . q7.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 31 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Eight Qubit Unit Cell
q0 q1 q2 q3
q4
q5
q6
q7
RO
CCJJ
LT
ICO
XCO
XCO
IPC

Take the CCJJ rf SQUID and stretch out its body.
Replicate four vertical qubits q0 . q3 spaced evenly apart.
Overlay four horizontal qubits q4 . q7.
Overlay internal couplers (ICO) at intersections of qubit bodies.
Overlay portions of external couplers (XCO) at extrema of qubits.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 31 / 45
Analog Components of a QA Processor Schematic Layout of Analog Components
Schematic Layout – Multiple Unit Cells

Larger processors are made by tiling the unit cell to the top, bottom, left,
and right. Shown is a 128-qubit 352-coupler array.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 32 / 45
Scalable Control and Readout Architecture
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 33 / 45
Scalable Control and Readout Architecture
Scalable Control and Readout Architecture
A 128-qubit processor requires 1632 control signals to operate. It is not
practical to rout one external bias per signal for many reasons:
Processor must be thermalized to a mixing chamber of a dilution
refrigerator, limited heat load.
Processor active circuit size O(mm2), limited room for passing signals
onto chip (wirebonds).
Limited space on chip available for wiring channels. Crosstalk is a
serious issue.
One needs to adopt more ecient strategies for controlling the processor:
Use programmable on-chip non-volatile memory to supply
time-independent biases.
Share currents for time-dependent biases among multiple devices
(works with superconducting circuits).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 34 / 45
Scalable Control and Readout Architecture
Control of Qubits and Couplers
Required signals:
5 static (but programmable) flux biases per qubit, 1 per coupler.
2 time-dependent current biases per qubit.

CCJJ Minor
DAC
CCJJ Minor
DAC
L Tuner
DAC
|Iq | Comp.
DAC
p
Qubit Flux
DAC
Coupler
DAC
Ig(t)
Iccjj(t)
Fccjj
x Qubit
Coupler
We use programmable magnetic memory (PMM) to provide static fluxes
and shared current biases to provide the time-dependent signals.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 35 / 45
Scalable Control and Readout Architecture
Programmable Magnetic Memory (PMM)
Static flux biases provided by digital-to-analog converters (DACs). Inputs
to DACs store integer flux quanta (0 = h/2e). DACs are addressable by
using a demultiplexing circuit that routs single flux quanta (SFQ). Memory
is non-volatile and demultiplexing circuit is 몈uiet?when not in use.

See Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 36 / 45
Scalable Control and Readout Architecture
Global Analog Bias Lines
Sharing of current bias lines between multiple qubits provides a significant
reduction in the number of external biases needed to run the processor.
Annealing Bias Iccjj(t)

Iccjj(t)
CCJJ
Qubit 1
CCJJ
Qubit 2
CCJJ
Qubit n

I p
q
-Compensation Bias Ig (t) = α
I p
q (t)
Ig(t)
Body
Qubit 1
Body
Qubit 2
Body
Qubit n
M1 M2 Mn
See Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 37 / 45
Scalable Control and Readout Architecture
XY Addressable Readout
Use a single common QFP latch across entire chip. Share dc SQUID
current (flux) biases as columns (rows).

c
c
c
c
c
c
c
c
Current Bias
Column 1
Current Bias
Column 2
Flux Bias
Row 1
Flux Bias
Row 2
QFP Latch
RO11 RO12
RO21 RO22
See Berkley et al., arXiv:0905.0891 for details.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 38 / 45
Scalable Control and Readout Architecture
Complete Eight Qubit Unit Cell
q0 q1 q2 q3
q4
q5
q6
q7
RO
CCJJ
LT
ICO
XCO
XCO
IPC
q
0
q
1 q2 q3
q4
100 mm
q5
q6
q7

Complete unit cell with PMM circuitry.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 39 / 45
Scalable Control and Readout Architecture
Complete Multiple Unit Cells

Complete 128-qubit chip with PMM circuitry.
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 40 / 45
Scalable Control and Readout Architecture
A Scalable QA Processor Architecture
How well does the architecture scale?

Element Count
Qubits 128
Couplers 352
QFPs 128
dc SQUIDs 128
PMM 992
A 128-qubit processor requires only 84 dierential external biases to
calibrate and operate (compare with the initial estimate of 1632).
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 41 / 45
Scalable Control and Readout Architecture
Not Covered in this Presentation . . .
There are many other parts needed
to realize a functional QA processor:
Circuit Design and Layout
Fabrication
Cryogenics
Wiring/Filtering
Magnetic Shielding
Room Temperature
Electronics
Calibration Methods
Software
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 42 / 45
Summary
Outline
1 Introduction to Quantum Annealing (QA)
2 Analog Components of a QA Processor
Qubits (Quantum Ising Spins)
Interqubit Couplers
Persistent Current Compensation
Inductance Tuner
Readout
Schematic Layout of Analog Components
3 Scalable Control and Readout Architecture
4 Summary
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 43 / 45
Summary
Summary
Key conclusions thusfar:
An architecture that enables quantum annealing of a lattice of
coupled flux qubits has been described.
A scalable control and readout architecture has been developed.
Prototype processors based upon this design have been fabricated.
Does it work? This is the topic of Part II . . .
Copyright, D-Wave Systems (2010) QA Processor Design September 2010 44 / 45
Summary
Useful References
Qubits
Harris et al. Phys. Rev. B, 81 134510 (2010).
Couplers
Harris et al. Phys. Rev. B, 80 052506 (2009).
Scalable Control Circuitry
Johnson et al., Supercond. Sci. Technol. 23, 065004 (2010).
XY-Addressable Readout
Berkley et al., arXiv:0905.0891 (2009).
(accepted in Supercond. Sci. Technol.)
Unit Cell Architecture
Harris et al., Phys. Rev. B 82, 024511 (2010).

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